1. Field of the Invention
The present invention relates to a storage device including a non-volatile memory and an information processing system, more particularly relates to speedup of data transfer in a storage device including a flash memory.
2. Description of the Related Art
In recent years, as a storage medium of a digital still camera or mobile computer device, attention is paid to a flash memory.
A flash memory is a semiconductor memory using tunneling or hot electron acceleration to make electrons pass through a gate insulation film and injecting them into a floating gate or trap layer to make a threshold value of a cell transistor change and thereby make it store data. A memory cell can be configured by just one transistor using a stacked gate structure, an MNOS structure, etc., therefore a cheap and large capacity memory can be realized. As a representative example, a NAND type flash memory can be explained.
FIG. 1 is a diagram of an example of the internal configuration of a NAND type flash memory. The NAND type flash memory of FIG. 1 has a plurality of memory units 1-1 to 1-n connected to bit lines BL1 to BLn arranged in an array (vertically and laterally). For example, the gate of a selection transistor 2 is connected to a selection gate line SL1, and gates of selection transistors 3 are connected to a selection gate line SL2. Further, gates of memory cells N0 to N15 are connected to word lines WL0 to WL15.
The memory cells N0 to N15 have stacked gate structures and store data according to charge accumulation in the floating gates. Namely, when many electrons are accumulated in the floating gates, the threshold values of the transistors rise, therefore the presence of current passing through the memory units 1 (-1 to -n) from the charged bit lines BL1 to BLn is detected by an access circuit 4 including a sense amplifier etc. to determine the data.
Such a NAND type flash memory does not require that a contact region be provided to the bit line for each memory cell, therefore is suitable for a medium of a particularly large capacity and cheap storage device.
In general, the programming speed of a flash memory is very slow. Several hundred microseconds are required per cell. Further, data cannot be overwritten, therefore it is necessary to erase data before the programming. A time of as long as several microseconds is required for this. This problem is treated by processing many memory cells in parallel.
Namely, by simultaneously writing data in a group of memory cells 5 connected to for example the same word line WL0 and forming a page unit and further erasing a cell block 6 configured by the groups of pages sharing the memory unit, a transfer speed of the program is improved.
Specifically, a 1 Gb NAND type flash memory is described in for example ISSCC 2002 Preprints, p. 106, Session 6.4. The page size is set to 2 kbytes, and the erase block size is set to 128 kB. Namely, by erasing a group of memory cells of 128 k bytes in parallel in one memory array and programming the memory cells there for each 2 k bytes in parallel, a program transfer speed of 10 MB/s is realized.
On the other hand, high speed non-volatile memories other than flash memories have been proposed in recent years. As a representative example thereof, a ferroelectric memory can be explained. The cell structure and operation of the ferroelectric memory now the mainstream were proposed in S. Sheffield et al. in ISSCC 2002 Preprints, p. 106, Session 6.4.
FIG. 2 is a circuit diagram of an example of the configuration of a ferroelectric memory disclosed in U.S. Pat. No. 4,873,664 etc.
This ferroelectric memory 10 configures a memory cell by one access transistor 11 and one ferroelectric capacitor 12 and stores a binary value, that is, 1 bit, according to a polarization direction of the ferroelectric capacitor 12. Further, in FIG. 2, BL11 and BL12 indicate bit lines, WL11 indicates a word line, PL11 indicates a plate line, 13 indicates a word line decoder and driver (WLDD), 14 indicates a plate line decoder and driver (PLDD), and 15 indicates a sense amplifier.
For example, in the ferroelectric memory 10, when the word line WL11 is selected and a pulse is applied to the plate line PL11, a read signal appears in the bit line BL11 connected to a counter electrode of the ferroelectric capacitor 12 of the memory cell.
Further, there are several variations in the form of the ferroelectric memory. Japanese Unexamined Patent Publication (Kokai) No. 09-116107 proposes another example.
The inversion of the polarization of the ferroelectric memory is realized in several nanoseconds by just applying 2V to 3V between capacitor electrodes. Accordingly, high speed writing at a cell level is possible, and in addition the power consumption is small. Further, the number of rewrites exceeds 1E10 or larger than that of a flash memory by several orders of magnitude.
Further, as high speed non-volatile memories, other than a ferroelectric memory, a magnetic random access memory (MRAM) using a ferroelectric material, an ovonic unified memory (OUM) using a phase change material, a RRAM, etc. have been proposed.
An MRAM is a semiconductor memory storing data according to a difference in spin direction of ferroelectric films and for example is described by R. Scheuerlein et al. in Digests of Papers of ISSCC 2000, p. 128. An OUM is a semiconductor memory storing data by phase transition of for example a chalcogenide film and is described by S. Lai et al. in Digests of Papers of IEDM 2001, p. 803. An RRAM is a semiconductor memory storing data by resistance hysteresis of a magnetoresistance effect material and is described by W. W. Zhuang et al. in Digest of Papers of IEDM 20021, 7.5. All of these non-volatile memories have higher performances than that of a flash memory in the access speed of the cell level and the number of rewrites by several orders of magnitude.